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module add4(add_a,add_b,sum,flow,clk,carry);

output [3:0] sum; //声明输出信号sum

output flow; //声明输出高位进位float

input [3:0] add_a,add_b; //声明两个4位二进制的输入信号add_a与add_b

input carry; //声明输入信号低位进位信号carry

input clk; //声明时钟信号CLK

reg [3:0] sum; //定义了一个4位的名为SUM的寄存器

reg flow; //定义了一个1位的名为FLOW的寄存器

always@(negedge clk) //CLK下降沿时，执行下列语句

begin

sum<=add_a+add_b+carry;//sum<=add_a+add_b+carry;

end

always@(posedge clk) //CLK上升沿时，执行下列语句

begin

flow<=(add_a[3]&add_b[3])|((add_a[3]|add_b[3])&sum[3]<1);

end //计算FLOW的数值

endmodule

module add4_test;

reg [3:0] add_a,add_b;

reg carry;

reg clk;

wire [3:0] sum;

wire flow;

add4 add4(add_a,add_b,sum,flow,clk,carry);

initial begin

carry=0;

clk=1;

add_a=4'b1011;

add_b=4'b0101;

end

always #1 clk=~clk; //产生时钟信号

always #5 carry=~carry; //间隔5，低位进位信号改变数值

always@(posedge clk)

begin

add_a<=add_b+1;

add_b<=add_a+1; //改变add_a与add_b

end

endmodule

module clkgen(clk,clk1,fetch,alu_clk);

output clk1,fetch,alu_clk; //声明输出变量clk1,fetch,alu_clk

input clk; //声明时钟信号clk

reg clk2,clk4,fetch; //定义3个1位寄存器名为clk2,clk4,fetch

initial //初始化

begin

clk2=0;

clk4=1;

fetch=0;

end

assign clk1=~clk; //逻辑功能定义

assign alu_clk=clk2&clk4&!fetch;

always@(posedge clk1) //每当clk1的信号出现上升沿时，下列语句被不断重复执行

begin

clk2<=~clk2;

end

always@(negedge clk2)

begin

clk4<=~clk4;

end

always@(posedge clk4)

begin

fetch<=~fetch;

end

endmodule

module clkgen_test;

reg clk;reg clk2;reg clk4;

clkgen clkgen(clk,clk1,fetch,alu_clk);

initial

begin

clk=1;

end

always #1 clk=~clk; //信号反相，#1表示延迟1个时间单位。

endmodule

module datactl(data,in,data_ena);

output[7:0] data;

input[7:0] in;

input data_ena; //声明输入输出

assign data=(data_ena)?in:8'bzzz_zzzz;//当data_ena为真，则允许输出，否则

//呈现高阻态

endmodule

module datactl_test;

wire [7:0] data;

reg [7:0] in;

reg data_ena;

datactl datactl(data,in,data_ena);

initial begin

data_ena=0;

in<=8'b0101_0101;

end

always #1 data_ena=~data_ena; //间隔2ns，data_ena改变

always #1 in=in+1; //间隔1ns，in的值在原来的基础上增1

endmodule

module machinectl(ena,fetch,rst);

output ena;

input fetch,rst; //声明输入和输出

reg ena; //定义ena的寄存器

always @(posedge fetch or posedge rst)//当fetch或者rst信号出现上升沿时，

begin //根据rst的值确定ena的值

if(rst)

ena<=0;

else

ena<=1;

end

endmodule

module machine(inc_pc,load_acc,load_pc,rd,wr,load_ir,datactl_ena,

halt,clk1,zero,ena,opcode);

output inc_pc,load_acc,load_pc,rd,wr,load_ir;

output datactl_ena,halt;

input clk1,zero,ena;

input [2:0] opcode;

reg inc_pc,load_acc,load_pc,rd,wr,load_ir;

reg datactl_ena,halt;

reg [2:0] state; //声明输入输出，以及定义寄存器

parameter //用parameter来定义标识符形式的常量

HLT=3'b000,

SKZ=3'b001,

ADD=3'b010,

ANDD=3'b011,

XORR=3'b100,

LDA=3'b101,

STO=3'b110,

JMP=3'b111;

always @(negedge clk1)

begin

if(!ena) //如果接收到复位信号RST，进行复位操作

begin

state<=3'b000;

{inc_pc,load_acc,load_pc,rd}<=4'b0000;

{wr,load_ir,datactl_ena,halt}<=4'b0000;

end

else

ctl_cycle; //执行任务ctl_cycle

end

//------------task ctl_cycle------------任务开始---------

task ctl_cycle;

begin

casex(state) //case语句

0: //rd与load_ir均为高电平，其余为低电平。指令寄存器寄

Begin //存由ROM送来的高8位指令代码

{inc_pc,load_acc,load_pc,rd}<=4'b0001;

{wr,load_ir,datactl_ena,halt}<=4'b0100;

state<=1;

end

1: //INC_PC从0变为1，故PC增1，ROM送来低8位指令代码，

Begin //指令寄存器寄存该8位代码

{inc_pc,load_acc,load_pc,rd}<=4'b1001;

{wr,load_ir,datactl_ena,halt}<=4'b0100;

state<=2;

end

2: //空操作

Begin

{inc_pc,load_acc,load_pc,rd}<=4'b0000;

{wr,load_ir,datactl_ena,halt}<=4'b0000;

state<=3;

end

3: //PC增1，指向下一条指令

begin

if(opcode==HLT) //若操作符为HLT，则输出信号HLT为高

begin

{inc_pc,load_acc,load_pc,rd}<=4'b1000;

{wr,load_ir,datactl_ena,halt}<=4'b0001;

end

else //否则其他各控制线输出为零。

begin

{inc_pc,load_acc,load_pc,rd}<=4'b1000;

{wr,load_ir,datactl_ena,halt}<=4'b0000;

end

state<=4;

end

4:

begin

if(opcode==JMP) //若为JMP，将目的地址送给程序计数器

begin

{inc_pc,load_acc,load_pc,rd}<=4'b0010;

{wr,load_ir,datactl_ena,halt}<=4'b0000;

end

else

if(opcode==ADD||opcode==ANDD||opcode==XORR||opcode==LDA)

begin //若操作符号为ANDD,ADD,XORR或LDA，读相应地址的数据

{inc_pc,load_acc,load_pc,rd}<=4'b0001;

{wr,load_ir,datactl_ena,halt}<=4'b0000;

end

else

if(opcode==STO) //若为STO，输出累加器数据

begin {inc_pc,load_acc,load_pc,rd}<=4'b0000;

{wr,load_ir,datactl_ena,halt}<=4'b0010;

end

else

begin //其他则为空操作

{inc_pc,load_acc,load_pc,rd} <=4'b0000;

{wr,load_ir,datactl_ena,halt}<=4'b0000;

end

state<=5;

end

5:

begin

if(opcode==ADD||opcode==ANDD||opcode==XORR||opcode==LDA)

begin //若操作符为ANDD,ADD,XORR，算术运算器就进行相应的运算

{inc_pc,load_acc,load_pc,rd} <=4'b0101;

{wr,load_ir,datactl_ena,halt}<=4'b0000;

end

else

if (opcode==SKZ&&zero==1) //若为SKZ，线判断累加器的值是否为0，如果为，

begin // PC增1，否则保持原值

{inc_pc,load_acc,load_pc,rd} <=4'b1000;

{wr,load_ir,datactl_ena,halt}<=4'b0000;

end

else

if(opcode==JMP) //若为JMP，锁存目的地址

begin

{inc_pc,load_acc,load_pc,rd} <=4'b1010;

{wr,load_ir,datactl_ena,halt}<=4'b0000;

end

else

if(opcode==STO) //若为STO，将数据写入地址处

begin

{inc_pc,load_acc,load_pc,rd} <=4'b0000;

{wr,load_ir,datactl_ena,halt}<=4'b1010;

end

else

begin //其他则为空操作

{inc_pc,load_acc,load_pc,rd} <=4'b0000;

{wr,load_ir,datactl_ena,halt}<=4'b0000;

end

state<=6;

end

6:

begin

if(opcode==STO) //若为STO，将数据写入地址处

begin

{inc_pc,load_acc,load_pc,rd} <=4'b0000;

{wr,load_ir,datactl_ena,halt}<=4'b0010;

end

else

if(opcode==ADD||opcode==ANDD||opcode==XORR||opcode==LDA)

begin //若操作符号为ANDD,ADD,XORR或LDA，读相应地址的数据

{inc_pc,load_acc,load_pc,rd} <=4'b0001;

{wr,load_ir,datactl_ena,halt}<=4'b0000;

end

else //其余为空操作

begin

{inc_pc,load_acc,load_pc,rd} <=4'b0000;

{wr,load_ir,datactl_ena,halt}<=4'b0000;

end

state<=7;

end

7:

begin

if(opcode==SKZ&&zero==1) //若操作符为SKZ且累加器值为0，

begin //则PC值再增加1，跳过一条指令，否则PC无变化

{inc_pc,load_acc,load_pc,rd} <=4'b1000;

{wr,load_ir,datactl_ena,halt}<=4'b0000;

end

else

begin

{inc_pc,load_acc,load_pc,rd} <=4'b0000;

{wr,load_ir,datactl_ena,halt}<=4'b0000;

end

state<=0;

end

default: //缺省为空操作

begin

{inc_pc,load_acc,load_pc,rd} <=4'b0000;

{wr,load_ir,datactl_ena,halt}<=4'b0000;

state<=0;

end

endcase

end

endtask

//-------------end of task ctl_cycle-----任务结束-----------------

endmodule

module control(clk1, zero, fetch, rst, opcode, inc_pc, load_acc, load_pc, rd, wr, load_ir, halt, datactl_ena);

output inc_pc,load_acc,load_pc,rd,wr,load_ir;

output datactl_ena,halt;

input clk1,zero,fetch,rst;

input [2:0] opcode; //声明输入和输出

wire ena; //定义wire类型的ena

machinectl machinectl(.fetch(fetch),.rst(rst),.ena(ena));

machine machine(.clk1(clk1),.zero(zero),.opcode(opcode), .ena(ena),.inc_pc(inc_pc),.load_acc(load_acc),.load_pc(load_pc),

.rd(rd),.wr(wr),.load_ir(load_ir),.halt(halt),.datactl_ena(datactl_ena)); //将machinectl与machine连接起来

//machinectl.v与machine.v均为上层文件

endmodule

module control_test;

wire inc_pc ,load_acc ,load_pc, rd, wr ,load_ir ,datactl_ena, halt;

wire clk1,fetch,alu_clock;

reg zero, rst;

reg [2:0] opcode;

reg clk;

clkgen clkgen(clk,clk1,fetch,alu_clk);

//用一个CLKGEN部件来产生clk1,fetch序列

control control(clk1, zero, fetch, rst, opcode, inc_pc, load_acc, load_pc, rd, wr, load_ir, halt, datactl_ena);

initial begin

rst=0;

clk=1;

zero=0;

opcode=3'b000;

end

always #1 clk=~clk; //产生时钟信号,1个时钟周期为2nm

always #160 zero=~zero;

always #16 opcode<=opcode+1;//经过8个时钟信号周期,opcode改变一次

endmodule

module cpu(rst,clk,rd,wr,halt,addr,data);

input rst;

input clk;

output rd;

output wr;

output halt;

output [12:0] addr;

output [7:0] data;

wire clk1 ，fetch ，alu_clk;

wire [15:0] opc_iraddr;

wire [7:0] accum_data;

wire [7:0] alu_out;

wire zero，inc_pc， load_acc， load_pc，load_ir， datactl_ena;

wire [12:0] pc_addr;

wire [7:0] data_altera;

register register26p(.opc_iraddr(opc_iraddr), .data(data_altera), .ena(load_ir), .clk1(clk1), .rst(rst));

clkgen clkgen27p(.clk(clk), .clk1(clk1), .fetch(fetch), .alu_clk(alu_clk));

accum accum1p(.accum(accum_data), .data(alu_out), .ena(load_acc), .clk1(clk1), .rst(rst));

datactl datactl24p(.data(data_altera), .in(alu_out),.data_ena(datactl_ena));

adr adr22p(.addr(addr), .fetch(fetch), .ir_addr(opc_iraddr[12:0]), .pc_addr(pc_addr));

counter counter11p( .pc_addr(pc_addr), .ir_addr(opc_iraddr[12:0]), .load(load_pc), .clock(inc_pc), .rst(rst));

alu alu15p(.alu_out(alu_out), .zero(zero), .data(data_altera), .accum(accum_data), .alu_clk(alu_clk), .opcode(opc_iraddr[15:13]));

control control12p(.clk1(clk1), .zero(zero), .fetch(fetch), .rst(rst), .opcode(opc_iraddr[15:13]),.inc_pc(inc_pc), .load_acc(load_acc), .load_pc(load_pc), .rd(rd), .wr(wr), .load_ir(load_ir), .halt(halt), .datactl_ena(datactl_ena));

assign data = data_altera;

endmodule

module sig(clk);

output clk;

reg clock;

initial

begin

clock=0;

end

assign clk=clock;

always #1 clock=~clock;

endmodule

module risc(rst);

reg rst;

wire clk, read, write, halt;

wire [7:0] data;

wire [12:0] addr;

wire ramsel, romsel;

sig sys_sig5p(.clk(clk));

cpu sys_rsc4p(.rst(rst),.clk(clk),.rd(read),.wr(write),.halt(halt),.addr(addr[12:0]),.data(data[7:0]));

ram sys_ram3p(.data(data[7:0]),.addr(addr[9:0]), .ena(ramsel), .read(read), .write(write));

rom sys_rom1p(.addr(addr[12:0]),.ena(romsel), .read(read), .data(data[7:0]));

addr_decode sys_addr_decode2p(.addr(addr[12:0]), .romsel(romsel), .ramsel(ramsel));

endmodule

//------------------------rscsys_ex1.v-------------------------------

`define VLP vlog1

`define PERIOD 100 //matches clkgen/vlog_behaviorial/verilog.v

module rscsys_ex1;

reg reset_req;

integer test;

reg [(3*8):0] mnemonic; //array that holds 3 8-bit ASCII characters

reg [12:0] PC_addr,IR_addr;

assign `VLP.rst =reset_req;

risc vlog1(rst);

initial //display time in nanoseconds

begin

$timeformat(-9,1,"ns",12);

display_debug_message;

end

always @(posedge `VLP.halt) // STOP when HALT instruction decoded

begin

#500

$display("\n************************************");

$display("*A HALT INSTRUCTION WAS PROCESSED!!! *");

$display("************************************\n");

display_debug_message;

end

task display_debug_message;

begin

$display("\n************************************");

$display("*THE FOLLOWING DEBUG TASK ARE AVAILABLE: *");

$display("* test1 to load the 1st diagnostic program. *");

$display("* test2 to load the 2nd diagnostic program. *");

$display("* test3 to load the Fibonacci program.*");

$display("************************************\n");

test1;

test2;

test3;

$stop;

end

endtask

task test1;

begin

test = 0;

disable MONITOR;

$readmemb("test1.pro",`VLP.sys_rom1p.memory);

$display("rom loaded successfully!");

$readmemb("test1.dat",`VLP.sys_ram3p.ram);

$display("ram loaded successfully!");

#1 test = 1;

sys_reset;

end

endtask

task test2;

begin

test = 0;

disable MONITOR;

$readmemb("test2.pro",`VLP.sys_rom1p.memory);

$display("rom loaded successfully!");

$readmemb("test2.dat",`VLP.sys_ram3p.ram);

$display("ram loaded successfully!");

#1 test = 2;

sys_reset;

end

endtask

task test3;

begin

test = 0;

disable MONITOR;

$readmemb("test3.pro",`VLP.sys_rom1p.memory);

$display("rom loaded successfully!");

$readmemb("test3.dat",`VLP.sys_ram3p.ram);

$display("ram loaded successfully!");

#1 test = 3;

sys_reset;

end

endtask

task sys_reset;

begin

reset_req = 0;

#(`PERIOD * 0.7) reset_req = 1;

#(1.5 * `PERIOD) reset_req = 0;

end

endtask

always @(test)

begin: MONITOR

case (test)

1: begin // display results when running test 1

$display("\n*** RUNNING CPUtest1 ----The Basic CPU Diagnostic Program ***");

$display("\n TIME PC INSTR ADDR DATA");$display("-------");

while(test==1)

@(`VLP.sys_rsc4p.adr22p.pc_addr)

if((`VLP.sys_rsc4p.adr22p.pc_addr%2==1)&&(`VLP.sys_rsc4p.adr22p.fetch==1))

begin

#60 PC_addr<=`VLP.sys_rsc4p.adr22p.pc_addr-1;

IR_addr<=`VLP.sys_rsc4p.adr22p.ir_addr;

#340 $strobe("%t %h %s %h %h",

$time,PC_addr,mnemonic,IR_addr,`VLP.data);

end

end

2:begin

$display("\n***RUNNING CPUtest2-The ad cpu program***");

$display("\n time pc instr addr data");

$display("-------------------------");

while(test==2)

@(`VLP.sys_rsc4p.adr22p.pc_addr)

if((`VLP.sys_rsc4p.adr22p.pc_addr%2==1)&&(`VLP.sys_rsc4p.adr22p.fetch==1))

begin

#60 PC_addr<=`VLP.sys_rsc4p.adr22p.pc_addr-1;

IR_addr<=`VLP.sys_rsc4p.adr22p.ir_addr;

#340 $strobe("%t %h %s %h %h",

$time,PC_addr,mnemonic,IR_addr,`VLP.data);

end

end

3:begin

$display("\n***RUNNING CPUtest3- an executable program***");

$display("***this pro should calculate the fibaci");

$display("***no sequence from 0 to 144***");

$display("\nTIME FIBOCI NO");

$display("-------------------------");

while(test==3)

begin

wait(`VLP.sys_rsc4p.alu15p.opcode==3'h1)

$strobe("%t %d",$time,`VLP.sys_ram3p.ram[10'h2]);

wait(`VLP.sys_rsc4p.alu15p.opcode!=3'h1);

end

end

endcase

end

always@(`VLP.sys_rsc4p.alu15p.opcode)

case(`VLP.sys_rsc4p.alu15p.opcode)

3'h0 :mnemonic="HLT";

3'h1 :mnemonic="SKZ";

3'h2 :mnemonic="ADD";

3'h3 :mnemonic="AND";

3'h4 :mnemonic="XOR";

3'h5 :mnemonic="LDA";

3'h6 :mnemonic="STO";

3'h7 :mnemonic="JMP";

default : mnemonic="???";

endcase

endmodule